This invention relates to a circuit arrangement for use in distributing a plurality of input signals to a plurality of memory addresses, a plurality of array processors, or the like.
Various attempts have been made to connect a plurality of transmission ends to a plurality of reception ends. In an information processing system comprising a central processing unit and a memory, a plurality of memory addresses of the memory are often accessed by the central processing unit so as to distribute a plurality of parallel data signals, such as vector data signals, from the central processing unit to the memory.
A similar operation is also carried out in a data processing system comprising a plurality of processing array elements and a control computer for controlling all of the processing array elements. Specifically, a plurality of transmission signals may be transmitted in parallel from the control computer to selected ones of the processing array elements.
Under the circumstances, a circuit arrangement or switching network must be placed between the transmission and the reception ends, such as the central processing unit, the memory, the control computer, the array elements, to form a connection path or paths therebetween.
In an article contributed by D. H. Lawrie to IEEE Transactions on Computers, Vol. C-24, No. 12 (December 1975), pages 1145-1155, and titled "Access and Alignment of Data in an Array Processor," a switching network is described which comprises a plurality of consecutively numbered input ports connected to the transmission ends, a plurality of consecutively numbered output ports connected to the reception ends, and a plurality of switching elements between the input and the output ports. The switching elements are divided into a plurality of stages which are interconnected in a perfect shuffle connection manner. With this structure, each input port can selectively be connected to all of the output ports through internal paths.
In order to selectively form the internal paths in the switching network, an input port number and an output port number are indicated by the transmission end to control the switching network each time when each input signal is transmitted from the transmission end to destined reception end or ends. In this event, each of the switching elements in question must calculate the input port number and the output port number in accordance with a predetermined algorithm to select a following one of the internal paths. Such operation is successively carried out in each stage for connection between input and output port indicated by the input and the output port numbers. In addition, each switching element must detect or monitor whether or not a conflict of the internal paths occurs on selection of the internal paths. This means that a complex control circuit is indispensable to every one of the switching elements included in the switching network. This results in an increase of hardware in the switching network.
Thus, control operation is decentralized or distributed to the respective switching elements. The decentralization of control operation may reduce performance of the switching network when a plurality of input signals must simultaneously be distributed to the corresponding output ports, as are the cases with the vector data signals.